Strix
64.1K

CVE-2026-90124

Unknown

Last modified

CVE-2026-90124 is a vulnerability of currently unknown severity. In the Linux kernel, the following vulnerability has been resolved: irqchip/renesas-rzg2l: Fix loss of interrupt rzg2l_clear_irq_int() and rzg2l_clear_tint_int() perform a read-modify-write on the ISCR/TSCR status registers to clear the bit for the interrupt just handled. Since these registers are write-0-to-clear per bit, this is racy: If another interrupt's status bit gets set between the read and the write, that bit is written back as 0 by the software-constructed value, clearing an interrupt that hasn't been serviced yet and losing it. This can be reproduced by triggering multiple interrupts at once, e.g.: gpioset -c gpiochip0 355=0 353=0 328=0 352=0 Fix this by writing back only the bit being cleared, with all other bits set to 1, instead of read-modify-writing the whole register.

Description

In the Linux kernel, the following vulnerability has been resolved: irqchip/renesas-rzg2l: Fix loss of interrupt rzg2l_clear_irq_int() and rzg2l_clear_tint_int() perform a read-modify-write on the ISCR/TSCR status registers to clear the bit for the interrupt just handled. Since these registers are write-0-to-clear per bit, this is racy: If another interrupt's status bit gets set between the read and the write, that bit is written back as 0 by the software-constructed value, clearing an interrupt that hasn't been serviced yet and losing it. This can be reproduced by triggering multiple interrupts at once, e.g.: gpioset -c gpiochip0 355=0 353=0 328=0 352=0 Fix this by writing back only the bit being cleared, with all other bits set to 1, instead of read-modify-writing the whole register. Since 1-bits are left unchanged by hardware, concurrently-set status bits for other interrupts are preserved.

Affected Software

Source: CNA advisory (CVE.org). NVD analysis pending.

VendorProductVersions
LinuxLinux>= 3fed09559cd8be79568d368ce02bf7f2d56259b6, < c043591f03a8111f7d306b8122c444a949486269; >= 3fed09559cd8be79568d368ce02bf7f2d56259b6, < b5ba8b861b5d833394bd23df3f4b59883ef18c88; >= 3fed09559cd8be79568d368ce02bf7f2d56259b6, < 3791e242ec2e5a5cd9e010a75ed1125d0e84d394; >= 3fed09559cd8be79568d368ce02bf7f2d56259b6, < 38c6831fefde0ff89f8d2dcb924f957a89dec414; >= 3fed09559cd8be79568d368ce02bf7f2d56259b6, < dbecbe23dc606c4af68b4591a41124186f5c1802; >= 3fed09559cd8be79568d368ce02bf7f2d56259b6, < 50b10bd0c2d721ad38abd1abe3acdefb6caa0944
LinuxLinux6.0

References

Timeline

Published
Last Modified
Status
Received

Frequently Asked Questions

What is CVE-2026-90124?
In the Linux kernel, the following vulnerability has been resolved: irqchip/renesas-rzg2l: Fix loss of interrupt rzg2l_clear_irq_int() and rzg2l_clear_tint_int() perform a read-modify-write on the ISCR/TSCR status registers to clear the bit for the interrupt just handled. Since these registers are write-0-to-clear per bit, this is racy: If another interrupt's status bit gets set between the read and the write, that bit is written back as 0 by the software-constructed value, clearing an interrupt that hasn't been serviced yet and losing it. This can be reproduced by triggering multiple interrupts at once, e.g.: gpioset -c gpiochip0 355=0 353=0 328=0 352=0 Fix this by writing back only the bit being cleared, with all other bits set to 1, instead of read-modify-writing the whole register. Since 1-bits are left unchanged by hardware, concurrently-set status bits for other interrupts are preserved.
How severe is CVE-2026-90124?
Severity scoring for CVE-2026-90124 is pending analysis.
How do I fix CVE-2026-90124?
Check the vendor references and advisories linked above for patched versions and mitigation guidance. You can also run a Strix scan to test if your systems are affected.

How Strix Helps

Related CVEs from 2026

View all 2026CVEs →

Are you affected by CVE-2026-90124?

Run a free Strix scan to check your systems for this vulnerability.

Scan your code now

Source: NVD / NIST